A continuing problem for VLSI testing is how to diagnose an exact location of a broken scan chain or chains. When there is low or zero yield, the scan chains are often broken so that the only opportunity to learn and diagnose the root cause of the problem is defect localization based upon scan chain failure data. Other test applications, such as, Level Sensitive Scan Design (LSSD), Logic Built In Self Test (LBIST), Array Built In Self Test (ABIST), functional, Design-For-Test (DFT) and Design-For-Diagnostics (DFD), all assume the scan chains are operational.
The problem of a broken scan chain or chains is usually encountered early in a technology life cycle and diagnostics is critical in improving the fabrication process so that manufacturing yield levels can be quickly achieved. An inability to improve the technology and yield can greatly impact a program or at least severely minimize the revenue that could be realized.
Rapid diagnosis to a location for Physical Failure Analysis (PFA) is needed to understand and correct process anomalies. In these low or zero yield situations, the most common failure is often the scan chain. The LSSD Flush and Scan tests will fail when there is one or more broken scan chains on a device. In these cases, there is no operating region where the scan chains are functional. Since most other tests utilize the scan chain to perform device tests, diagnostics of the broken scan chain or scan chains with hard DC flush and scan fails is extremely limited. Also as density of VLSI devices continue to increase, their respective scan chains will continue to increase in size proportionally and thus, this problem will become even more severe. Fault simulation/test generation, providing extremely vital tools for diagnosing combinational faults, is very inefficient and ineffective for shift register (SR) diagnostics. Hence, a solution is needed which speeds broken scan chain diagnostics on the majority of the failing devices to enable timely process corrections and yield improvements.
Existing methods and approaches to this problem include dumping megafail data on the tester, Automatic Test Pattern Generation (ATPG) directed at each hypothetical broken latch, voltage and timing sensitive methods, IDDQ walk current measurements, power up/down techniques, and LBIST/ABIST engine based techniques. Significant drawbacks are that the known solutions require very large data volumes, extremely long simulation times, and are not always 100% reliable, and further not one single known method is always successful all the time. This can be attributed to the nature of the particular fault and its manifestation, complex faults, and that faults are not limited to the type of chip area that propagates to system paths of the broken latch or latches whether it originates from combinational logic or array outputs.
A need thus exists for fast and efficient techniques that diagnose defects in a broken scan chain or chains and that facilitate defect localization for Physical Failure Analysis (PFA).